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? 2015-2016 microchip technology inc. ds00001855d-page 1 highlights ? usb hub feature contro ller ic with 4 usb 3.1 gen 1 / usb 2.0 downstream ports ? usb-if battery charger revision 1.2 support on up & downstream ports (dcp, cdp, sdp) ? usb link power management (lpm) support ? enhanced oem configuration options available through either otp or spi rom ? available in 56-pin (7 x 7 mm) vqfn lead-free, rohs compliant package ? commercial and industrial grade temperature support ? configuration straps: pr edefined configuration of system level functions target applications ? standalone usb hubs ? laptop docks ? pc motherboards ? pc monitor docks ? multi-function usb 3.1 gen 1 peripherals key benefits ? usb 3.1 gen 1 compliant 5 gbps, 480 mbps, 12 mbps and 1.5 mbps operation - 5 v tolerant usb 2.0 pins - 1.32 v tolerant usb 3.1 gen 1 pins - integrated termination & pul l-up/pull-down resistors ? supports per port battery charging of most popu- lar battery powered devices - usb-if battery charging rev. 1.2 support (dcp, cdp, sdp) -apple ? portable product charger emulation - chinese yd/t 1591-2006 charger emulation - chinese yd/t 1591-2009 charger emulation - european union universal mobile charger support - support for microchip usc100x family of battery charging controllers - supports additional portable devices ? smart port controller operation - firmware handling of companion port controllers ? on-chip microcontroller - manages i/os, vbus, and other signals ? 8 kb ram, 64 kb rom ? 8 kb one time programmable (otp) rom - includes on-chip charge pump ? configuration programming via otp rom, spi rom, or smbus ?portswap - configurable differential intro-pair signal swapping ?phyboost ? - programmable usb transceiver drive strength for recovering signal integrity ? varisense ? - programmable usb receiver sensitivity ? compatible with microsoft windows 8, 7, xp, apple os x 10.4+, and linux hub drivers ? optimized for low-power operation and low thermal dissipation ? package - 56-pin vqfn (7 x 7 mm) ? environmental - 3 kv hbm jesd22-a114f esd protection - commercial temperature range (0c to +70c) - industrial temperature range (-40c to +85c) usb5744 4-port ss/hs usb controller hub
usb5744 ds00001855d-page 2 ? 2015-2016 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current documentation to obtain the most up-to-date version of this document ation, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2015-2016 microchip technology inc. ds00001855d-page 3 usb5744 1.0 preface ................................................................................................................... ......................................................................... 4 2.0 introduction .............................................................................................................. ....................................................................... 6 3.0 pin description and configuration ......................................................................................... ......................................................... 8 4.0 device connections ........................................................................................................ .............................................................. 18 5.0 modes of operation ........................................................................................................ .............................................................. 20 6.0 device configuration ...................................................................................................... ............................................................... 23 7.0 device interfaces ......................................................................................................... ................................................................. 24 8.0 functional descriptions ................................................................................................... .............................................................. 25 9.0 operational charac teristics ............................................................................................... ............................................................ 31 10.0 package information ...................................................................................................... ............................................................. 40
usb5744 ds00001855d-page 4 ? 2015-2016 microchip technology inc. 1.0 preface 1.1 general terms table 1-1: general terms term description adc analog-to-digital converter byte 8 bits cdc communication device class csr control and status registers dword 32 bits eop end of packet ep endpoint fifo first in first out buffer fs full-speed fsm finite state machine gpio general purpose i/o hs hi-speed hsos high speed over sampling hub feature controller the hub feature controller, sometimes called a hub controller for short is the internal processor used to enable the unique features of the usb controller hub. this is not to be confused with the usb hub controller t hat is used to communicate the hub status back to the host during a usb session. i 2 c inter-integrated circuit ls low-speed lsb least significant bit lsb least significant byte msb most significant bit msb most significant byte n/a not applicable nc no connect otp one time programmable pcb printed circuit board pcs physical coding sublayer phy physical layer pll phase lock loop reserved refers to a reserved bit field or address. unless otherwise noted, reserved bits must always be zero for write operations. unle ss otherwise noted, va lues are not guaran- teed when reading reserved bits. unless ot herwise noted, do not read or write to reserved addresses. sdk software development kit smbus system management bus uuid universally unique identifier word 16 bits
? 2015-2016 microchip technology inc. ds00001855d-page 5 usb5744 1.2 reference documents 1. unicode utf-16le for string descriptors usb engineering change notice, december 29th, 2004, http:// www.usb.org 2. universal serial bus revision 3.1 specification , http://www.usb.org 3. battery charging specification , revision 1.2, dec. 07, 2010, http://www.usb.org 4. i 2 c-bus specification , version 1.1, http://www.nxp.com 5. system management bus specification , version 1.0, http://smbus.org/specs
usb5744 ds00001855d-page 6 ? 2015-2016 microchip technology inc. 2.0 introduction 2.1 general description the microchip usb5744 hub is low-power, oem configurable, usb 3.1 gen 1 hub feature controller with 4 downstream ports and advanced features for embedded usb applic ations. the usb5744 is fully compliant with the universal serial bus revision 3.1 specification and usb 2.0 link power management addendum . the usb5744 supports 5 gbps superspeed (ss), 480 mbps hi-speed (hs), 12 mbps full-speed (fs), and 1.5 mbps low-speed (ls) usb down- stream devices on all enabled downstream ports. the usb5744 supports the legacy usb speeds (hs/fs/ls) through a dedicated usb 2.0 hu b feature controller that is the culmination of five generations of microchip hub feature controller design and experience with proven reliability, interoperability, and device compatibility. the superspeed hub feature controller operates in parallel with the usb 2.0 controller, decoupli ng the 5 gbps ss data transfers from bottle necks due to the slower usb 2.0 traffic. the usb5744 supports downstream battery charging. the u sb5744 integrated battery charger detection circuitry sup- ports the usb-if battery charging (bc1.2) detection met hod and most apple devices. the usb5744 provides the bat- tery charging handshake and supports the following usb-if bc1.2 charging profiles: ? dcp: dedicated charging port (power brick with no data) ? cdp: charging downstream port (1.5a with data) ? sdp: standard downstream port (0.5a with data) ? custom profiles loaded via smbus or otp additionally, the usb5744 includes many powerful and unique features such as: portswap , which adds per-port programmability to usb differentia l-pair pin locations. portswap allows direct alignment of usb signals (d+/d-) to connectors to avoid uneven trace length or crossing of the usb differential signals on the pcb. phyboost , which provides programmable levels of hi-speed usb signal drive strength in the downstream port transceivers. phyboos t attempts to restore usb signal integrity in a compromised system environment. the gr aphic on the right shows an example of hi-speed usb eye diagrams before and after ph yboost signal integr ity restoration. in a compromised syst em environment varisense , which controls the usb receiver sensitivity enabling programmable levels of usb signal receive sensitivity. this capability allows operation in a sub-optimal system environment, such as when a captive usb cable is used. the usb5744 can be configured for operation through internal default settings. custom oem configurations are sup- ported through external spi rom or otp ro m. all port control signal pins are un der firmware control in order to allow for maximum operational flexibility, and are available as gpios for customer specific use. the usb5744 is available in commercial (0c to +70c) and industrial (-40c to +85c) temperature ranges. an internal block diagram of the usb5744 is shown in figure 2-1 .
? 2015-2016 microchip technology inc. ds00001855d-page 7 usb5744 figure 2-1: internal block diagram
usb5744 ds00001855d-page 8 ? 2015-2016 microchip technology inc. 3.0 pin description and configuration 3.1 pin assignments note 1: configuration straps are identified by an underlined sym bol name. signals that f unction as configurations traps must be augmented with an external re sistor when connected to a load. refer to section 3.4, "config- uration straps and programmable functions" for additional information. figure 3-1: 56-vqfn pin assignments note: exposed pad (vss ) on bottom of package must be connected to ground with a via field. (connect exposed pad to ground with a via field) vss usb5744 56-vqfn (top view) 4 5 6 7 8 9 10 11 2 2 39 38 37 36 35 34 33 32 5 3 usb3dn_rxdm1 usb3dn_rxdp1 usb2dn_dp2/prt_dis_p2 usb2dn_dm2/prt_dis_m2 usb3dn_txdp2 usb3dn_txdm2 vdd12 usb3dn_rxdp2 spi_ce_n/cfg_non_rem spi_di/cfg_bc_en spi_clk/smclk vdd12 vdd33 usb3dn_rxdm4 vbus_det spi_do/smdat 2 3 12 13 31 30 41 40 vdd12 usb3dn_txdm1 usb3dn_txdp1 usb2dn_dm1/prt_dis_m1 prt_ctl1 prt_ctl2 prt_ctl3 prt_ctl4/gang_pwr 1 usb2dn_dp1/prt_dis_p1 14 usb3dn_rxdm2 29 usb3dn_rxdp4 reset_n 42
? 2015-2016 microchip technology inc. ds00001855d-page 9 usb5744 table 3-1 details the package pin assignments in table format. table 3-1: 56-vqfn pin assignments pin number pin name pin number pin name 1 usb2dn_dp1/prt_dis_p1 29 usb3dn_rxdp4 2 usb2dn_dm1/prt_dis_m1 30 usb3dn_rxdm4 3 usb3dn_txdp1 31 vdd33 4 usb3dn_txdm1 32 prt_ctl4/gang_pwr 5 vdd12 33 vdd12 6 usb3dn_rxdp1 34 prt_ctl3 7 usb3dn_rxdm1 35 prt_ctl2 8 usb2dn_dp2/prt_dis_p2 36 prt_ctl1 9 usb2dn_dm2/prt_dis_m2 37 vbus_det 10 usb3dn_txdp2 38 spi_clk/smclk 11 usb3dn_txdm2 39 spi_do/smdat 12 vdd12 40 spi_di/cfg_bc_en 13 usb3dn_rxdp2 41 spi_ce_n/cfg_non_rem 14 usb3dn_rxdm2 42 reset_n 15 vdd12 43 vdd12 16 vdd33 44 vdd33 17 usb2dn_dp3/prt_dis_p3 45 usb2up_dp 18 usb2dn_dm3/prt_dis_m3 46 usb2up_dm 19 usb3dn_txdp3 47 usb3up_txdp 20 usb3dn_txdm3 48 usb3up_txdm 21 vdd12 49 vdd12 22 usb3dn_rxdp3 50 usb3up_rxdp 23 usb3dn_rxdm3 51 usb3up_rxdm 24 usb2dn_dp4/prt_dis_p4 52 atest 25 usb2dn_dm4/prt_dis_m4 53 xtalo 26 usb3dn_txdp4 54 xtali/clk_in 27 usb3dn_txdm4 55 vdd33 28 vdd12 56 rbias table 3-2: 56-vqfn pin assignments 1 usb2dn_dp1/prt_dis_p1 29 nc 2 usb2dn_dm1/prt_dis_m1 30 nc 3 usb3dn_txdp1 31 vdd33 4 usb3dn_txdm1 32 gpio20/gang_pwr
usb5744 ds00001855d-page 10 ? 2015-2016 microchip technology inc. 5 vdd12 33 vdd12 6 usb3dn_rxdp1 34 gpio19 7 usb3dn_rxdm1 35 prt_ctl2 8 usb2dn_dp2/prt_dis_p2 36 prt_ctl1 9 usb2dn_dm2/prt_dis_m2 37 vbus_det 10 usb3dn_txdp2 38 spi_clk/smclk 11 usb3dn_txdm2 39 spi_do/smdat 12 vdd12 40 spi_di/cfg_bc_en 13 usb3dn_rxdp2 41 spi_ce_n/cfg_non_rem 14 usb3dn_rxdm2 42 reset_n 15 vdd12 43 vdd12 16 vdd33 44 vdd33 17 nc 45 usb2up_dp 18 nc 46 usb2up_dm 19 nc 47 usb3up_txdp 20 nc 48 usb3up_txdm 21 vdd12 49 vdd12 22 nc 50 usb3up_rxdp 23 nc 51 usb3up_rxdm 24 nc 52 atest 25 nc 53 xtalo 26 nc 54 xtali/clk_in 27 nc 55 vdd33 28 vdd12 56 rbias table 3-2: 56-vqfn pin assignments (continued)
? 2015-2016 microchip technology inc. ds00001855d-page 11 usb5744 3.2 pin descriptions this section contains descriptions of the various usb5744 pins. this pin descriptions have been broken into functional groups as follows: ? usb 3.1 gen 1 pin descriptions ? usb 2.0 pin descriptions ? usb port contro l pin descriptions ? spi/smbus pin descriptions ? miscellaneous pin descriptions ? power and ground pin descriptions the ? _n ? symbol in the signal name indicates that the active, or a sserted, state occurs when the signal is at a low voltage level. for example, reset_n indicates that the reset signal is active low. when ? _n ? is not present after the signal name, the signal is asserted when at the high voltage level. the terms assertion and negation are used exclusively. this is done to avoid confusion when working with a mixture of ?active low? and ?active high? signals. the term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. t he term negate, or negation, indicates that a signal is inac- tive. note: the buffer type for each signal is indicated in the ?buffer type? column of the pin description tables. a description of the buffer types is provided in section 3.3, "buffer types," on page 15 . for additional information on configuration straps and configurable pins, refer to section 3.4, "configuration straps and programmable functions" . table 3-3: usb 3.1 gen 1 pin descriptions num pins symbol buffer type description 1 usb3up_txdp io-u usb 3.1 gen 1 upstream superspeed transmit data plus. 1 usb3up_txdm io-u usb 3.1 gen 1 upstream superspeed transmit data minus. 1 usb3up_rxdp io-u usb 3.1 gen 1 upstream superspeed receive data plus. 1 usb3up_rxdm io-u usb 3.1 gen 1 upstream superspeed receive data minus. 4 usbdn_txdp[4:1] io-u usb 3.1 gen 1 downst ream ports 4-1 superspeed transmit data plus. 4 usbdn_txdm[4:1] io-u usb 3.1 gen 1 downstream ports 4-1 superspeed transmit data minus. 4 usbdn_rxdp[4:1] io-u usb 3.1 gen 1 downstream ports 4-1 superspeed receive data plus. 4 usbdn_rxdm[4:1] io-u usb 3.1 gen 1 downstream ports 4-1 superspeed receive data minus. table 3-4: usb 2.0 pin descriptions num pins symbol buffer type description 1 usb2up_dp io-u usb 2.0 upstream data plus (d+). 1 usb2up_dm io-u usb 2.0 upstream data minus (d-).
usb5744 ds00001855d-page 12 ? 2015-2016 microchip technology inc. note 2: configuration strap values are latched on po wer-on reset (por) and the rising edge of reset_n (external chip reset). configuration straps are identified by an underlined symbol nam e. signals that function as con- figurations traps must be augmented with an external resistor when connected to a load. refer to section 3.4, "configuration straps and programmable functions" for additional information. 4 usb2dn_dp[4:1] io-u usb 2.0 downstream ports 4-1 data plus (d+). prt_dis_p[ 4 :1] i port 4-1 d+ disable configuration strap. these configuration straps are us ed in conjunction with the corre- sponding prt_dis_m[ 4 :1] straps to disable the related port (4-1). refer to section 3.4.2, "port disable configuration (prt_dis_p[4:1] / prt_dis_m[4:1])" for more information. see note 2 . 4 usb2dn_dm[4:1] io-u usb 2.0 downstream ports 4-1 data minus (d-). prt_dis_m[ 4 :1] i port 4-1 d- disable configuration strap. these configuration straps are us ed in conjunction with the corre- sponding prt_dis_p[ 4 :1] straps to disable the related port (4-1). refer to section 3.4.2, "port disable configuration (prt_dis_p[4:1] / prt_dis_m[4:1])" for more information. see note 2 . 1 vbus_det is this signal detects the stat e of the upstream bus power. when designing a detachable hub, this pin must be connected to the vbus power pin of the upstream usb port through a resistor divider (50 k ? by 100 k ? ) to provide 3.3 v. for self-powered applications with a permanently attached host, this pin must be connected to either 3.3 v or 5.0 v through a resistor divider to provide 3.3 v. in embedded applications, vbus_det may be controlled (toggled) when the host desires to renegotiate a connection without requiring a full reset of the device. gpio16 i/o6 general purpose input/output 16. table 3-5: usb port co ntrol pin descriptions num pins symbol buffer type description 1 prt_ctl1 i (pu) port 1 power enable / overcurrent sense. as an output, this signal is an active high control signal used to enable power to the downstream port 1. as an input, this signal indicates an overcurrent condition from an extern al current monitor on usb port 1. 1 prt_ctl2 i (pu) port 2 power enable / overcurrent sense. as an output, this signal is an active high control signal used to enable power to the downstream port 2. as an input, this signal indicates an overcurrent condition from an extern al current monitor on usb port 2. table 3-4: usb 2.0 pin descriptions (continued) num pins symbol buffer type description
? 2015-2016 microchip technology inc. ds00001855d-page 13 usb5744 note 3: configuration strap values are latched on po wer-on reset (por) and the rising edge of reset_n (external chip reset). configuration straps are identified by an underlined symbol name. signals that function as con- figurations traps must be augmented with an external resistor when connected to a load. refer to section 3.4, "configuration straps and programmable functions" for additional information. 1 prt_ctl3 i (pu) port 3 power enable / overcurrent sense. as an output, this signal is an ac tive high control signal used to enable power to the downstream port 3. as an input, this signal indicates an overcurrent condition from an extern al current monitor on usb port 3. 1 prt_ctl4 i (pu) port 4 power enable / overcurrent sense. as an output, this signal is an ac tive high control signal used to enable power to the downstream port 4. as an input, this signal indicates an overcurrent condition from an external current monitor on usb port 4. gang_pwr i (pu) when pulled high enables gang mode. gang power pin when used in gang mode. table 3-6: spi/smbus pin descriptions num pins symbol buffer type description 1 spi_ce_n o12 active low spi chip enable output. gpio7 i/o12 general purpose input/output 7. cfg_non_rem i non-removable port configuration strap. this configuration strap is used to configure the number of non- removable ports. refer to section 3.4.3, "non- removable port con- figuration (cfg_non_rem)" for more information. see note 3 . 1 spi_clk o6 spi clock output to the serial ro m, when configured for spi opera- tion. smclk od12 smbus clock pin, when configured for smbus slave operation. gpio4 i/o6 general purpose input/output 4. 1 spi_do o6 spi data output, when c onfigured for spi operation. smdat i/o12 smbus data pin, when configured for smbus slave operation. gpio5 i/o6 general purpose input/output 5. 1 spi_di is spi data input, when configured for spi operation. gpio9 i/o12 general purpose input/output 9. cfg_bc_en i battery charging configuration strap. this configuration strap is used to enable battery charging. refer to section 3.4.4, "battery charging configuration (cfg_bc_en)" for more information. see note 3 . table 3-5: usb port control pi n descriptions (continued) num pins symbol buffer type description
usb5744 ds00001855d-page 14 ? 2015-2016 microchip technology inc. table 3-7: miscellaneous pin descriptions num pins symbol buffer type description 1 reset_n is the reset_n pin puts the device into reset mode, as the name of the pin and function then align. 1 xtali iclk external 25 mhz crystal input clk_in iclk external reference clock input. the device may alternatively be driven by a single-ended clock oscil- lator. when this method is used, xtalo should be left unconnected. 1 xtalo oclk external 25 mhz crystal output 1 rbias ai a 12.0 k ? (+/- 1%) resistor is attached from ground to this pin to set the transceiver?s internal bias settings. 1 atest ai analog test pin. this signal is used for test purposes and must always be connected to ground. table 3-8: power and ground pin descriptions num pins symbol buffer type description 4 vdd33 p +3.3 v power and internal regulator input refer to section 4.1, "power connections" for power connection infor- mation. 8 vdd12 p +1.2 v core power refer to section 4.1, "power connections" for power connection infor- mation. pad vss p common ground. this exposed pad must be connect ed to the ground plane with a via array.
? 2015-2016 microchip technology inc. ds00001855d-page 15 usb5744 3.3 buffer types table 3-9: buffer types buffer type description i input is schmitt-triggered input o6 output with 6 ma sink and 6 ma source o12 output with 12 ma sink and 12 ma source od12 open-drain output with 12 ma sink pu 50 a (typical) internal pull-up. unless other wise noted in the pin description, internal pull- ups are always enabled. internal pull-up resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled high, an external resistor must be added. pd 50 a (typical) internal pull-down. unless ot herwise noted in the pin description, internal pull-downs are always enabled. internal pull-down resistors prevent unconnected inputs from floating. do not rely on internal resistors to drive signals external to the device. when connected to a load that must be pulled low, an external resistor must be added. io-u analog input/output as defined in usb specification ai analog input iclk crystal oscillator input pin oclk crystal oscillator output pin p power pin note: refer to section 9.5, "dc specifications" for individual buffer dc electrical characteristics.
usb5744 ds00001855d-page 16 ? 2015-2016 microchip technology inc. 3.4 configuration straps and programmable functions configuration straps are multi-functi on pins that are used during power-on reset (por) or external chip reset ( reset_n ) to determine the default configurati on of a particular feature. the state of the signal is latched following de- assertion of the reset. configuration straps are identified by an underlined symbol name. this section details the various device configuration straps and asso ciated programmable pin functions. 3.4.1 spi/smbus configuration the spi/smbus pins can be configured into one of two functional modes: ? spi mode ? smbus slave mode if 10 k ? pull-up resistors are detected on spi_do and spi_clk , the spi/smbus pins are configured into smbus slave mode. if no pull-ups or pull-downs are detected on spi_do and spi_clk , the spi/smbus pins are first configured into spi mode. the strap settings for t hese supported modes are detailed in table 3-10 . the individual pin function assign- ments for each mode are detailed in ta b l e 3 - 11 . for additional device connection information, refer to section 4.0, "device connections" . note 4: in order to use the spi interface, an spi rom containing a valid signature of 2dfu (device firmware upgrade) beginning at address 0xfffa must be present. refer to section 7.1, "spi master interface" for additional information. note: the system designer must guarantee that configuration stra ps meet the timing requirements specified in section 9.6.2, "power-o n and configuration strap timing," on page 35 and section 9.6.3, "reset and con- figuration strap timing," on page 36 . if configuration straps are not at the correct voltage level prior to being latched, the device may captur e incorrect strap values. table 3-10: spi/smbus mo de configuration settings pin spi mode ( note 4 ) smbus slave mode 39 ( spi_do ) no pull-up/down 10 k ? pull-up 38 ( spi_clk ) no pull-up/down 10 k ? pull-up table 3-11: spi/smbus mode pin assignments pin spi mode smbus slave mode 41 spi_ce_n cfg_non_rem 40 spi_di cfg_bc_en 39 spi_do smdat 38 spi_clk smclk
? 2015-2016 microchip technology inc. ds00001855d-page 17 usb5744 3.4.2 port disable configuration ( prt_dis_p[ 4 :1] / prt_dis_m[ 4 :1] ) the prt_dis_p[ 4 :1] and prt_dis_m[ 4 :1] configuration straps are used in conjunc tion to disable the related port (4-1). for prt_dis_p x (where x is the corresponding port 4-1): 0 = port x d+ enabled 1 = port x d+ disabled for prt_dis_m x (where x is the corresponding port 4-1): 0 = port x d- enabled 1 = port x d- disabled 3.4.3 non-removable po rt configuration ( cfg_non_rem ) the cfg_non_rem configuration strap is used to configure the no n-removable port settings of the device to one of five settings. these modes are selected by the configuration of an external resistor on the cfg_non_rem pin. the resistor options are a 200 k ? pull-down, 200 k ? pull-up, 10 k ? pull-down, 10 k ? pull-up, and 10 ? pull-down, as shown in table 3-12 . 3.4.4 battery charging configuration ( cfg_bc_en ) the cfg_bc_en configuration strap is used to co nfigure the battery charging port se ttings of the device to one of five settings. these modes are selected by the c onfiguration of an external resistor on the cfg_bc_en pin. the resistor options are a 200 k ? pull-down, 200 k ? pull-up, 10 k ? pull-down, 10 k ? pull-up, and 10 ? pull-down, as shown in table 3-13 . note: both prt_dis_p x and prt_dis_m x (where x is the corresponding port) must be tied to 3.3 v to disable the associated downstream port. disabling the usb 2.0 port will also disable the corresponding usb 3.1 gen 1 port. table 3-12: cfg_non_rem resistor encoding cfg_non_rem resistor value setting 200 k ? pull-down all ports removable 200 k ? pull-up port 1 non-removable 10 k ? pull-down port 1, 2 non-removable 10 k ? pull-up port 1, 2, 3, non-removable 10 ? pull-down port 1, 2, 3, 4 non-removable table 3-13: cfg_bc_en resistor encoding cfg_bc_en resistor value setting 200 k ? pull-down no battery charging 200 k ? pull-up port 1 battery charging 10 k ? pull-down port 1, 2 battery charging 10 k ? pull-up port 1, 2, 3, battery charging 10 ? pull-down port 1, 2, 3, 4 battery charging
usb5744 ds00001855d-page 18 ? 2015-2016 microchip technology inc. 4.0 device connections 4.1 power connections figure 4-1 illustrates the devi ce power connections. 4.2 spi rom connections figure 4-2 illustrates the device spi rom connections. refer to section 7.1, "spi mast er interface," on page 24 for additional information on this device interface. figure 4-1: power connections figure 4-2: spi rom connections +3.3v supply usb5744 3.3v internal logic vdd33 (4x) vss 1.2v internal logic +1.2v supply vdd12 (8x) usb5744 spi_ce_n spi_clk spi_do spi_di spi rom ce# clk do di
? 2015-2016 microchip technology inc. ds00001855d-page 19 usb5744 4.3 smbus slave connections figure 4-3 illustrates the device smbus slave connections. refer to section 7.2, "smbus slave interface," on page 24 for additional information on this device interface. figure 4-3: smbus slave connections +3.3v usb5744 smclk smdat smbus master clock data 10k +3.3v 10k
usb5744 ds00001855d-page 20 ? 2015-2016 microchip technology inc. 5.0 modes of operation the device provides two main modes of operation: standby mode and hub mode. these modes are controlled via the reset_n pin, as shown in ta b l e 5 - 1 . the flowchart in figure 5-1 details the modes of operation and details how the device traverses through the hub mode stages (shown in bold). the remaining sub-sections provide more detail on each stage of operation. table 5-1: modes of operation reset_n input summary 0 standby mode : this is the lowest power mode of the device. no functions are active other than monitoring the reset_n input. all port interfaces are high impedance and the pll is halted. refer to section 8.2.2, "external chip reset (reset_n)" for addi- tional information on reset_n . 1 hub (normal) mode : the device operates as a configurable usb hub with battery charger detection. this mode has various sub-modes of operation, as detailed in figure 5-1 . power consumption is based on the numb er of active ports, their speed, and amount of data received. figure 5-1: hub mode flowchart combine otp config data in spi mode & ext. spi rom present? yes no run from external spi rom (spi_init) smbus host present? reset_n deasserted modify config based on config straps (cfg_rd) load config from internal rom yes no (strap) perform smbus/i 2 c initialization soc done? yes no (soc_cfg) (otp_cfg) hub connect (hub.connect) normal operation
? 2015-2016 microchip technology inc. ds00001855d-page 21 usb5744 5.1 boot sequence 5.1.1 standby mode if the reset_n pin is asserted, the hub will be in standby mode. this mode provides a very low power state for maxi- mum power efficiency when no signaling is required. this is the lowest power state. in standby mode all downstream ports are disabled, the usb data pins are held in a high-im pedance state, all transactions immediately terminate (no states saved), all internal registers return to their default st ate, the pll is halted, and core logic is powered down in order to minimize power consumption. because core logic is pow ered off, no configuration settings are retained in this mode and must be re-initialized after reset_n is negated high. 5.1.2 spi initializati on stage (spi_init) the first stage, the initialization st age, occurs on the deassertion of reset_n . in this stage, the internal logic is reset, the pll locks if a valid clock is supplied, and the configuration registers are initialized to t heir default state. the interna l firmware then checks for an external spi rom. the firmware looks for an external spi flash device that contains a valid signature of ?2dfu? (device firmware upgrade) beginning at address 0xfffa. if a valid signature is found, then the external rom is enabled and the code execution begins at addre ss 0x0000 in the external spi device. if a valid signa- ture is not found, then execution cont inues from internal rom (cfg_rd stage). when using an external spi rom, a 1 mbit, 60 mhz or faster rom must be used. both 1- and 2-bit spi operation are supported. for optimum thr oughput, a 2-bit spi rom is recommended. bo th mode 0 and mode 3 spi roms are also supported. if the system is not strapped for spi mode, code ex ecution will continue from internal rom (cfg_rd stage). 5.1.3 configuration read stage (cfg_rd) in this stage, the internal firmware loads the default values from the internal rom and th en uses the conf iguration strap- ping options to override the default values. refer to section 3.4, "configuration straps and programmable functions" for information on usage of the va rious device configuration straps. 5.1.4 strap read stage (strap) in this stage, the firmware registers the configuration strap settings on the spi_do and spi_clk pins. refer to section 3.4.1, "spi/smbus configuration" for information on configuring these stra ps. if configured for smbus slave mode, the next state will be soc_cfg. otherwi se, the next state is otp_cfg. 5.1.5 soc configuration stage (soc_cfg) in this stage, the soc can modify any of the default configur ation settings specified in the integrated rom, such as usb device descriptors and port electrical settings. there is no time limit on this mode. in this stage the firmware will wait indefinitely for the smbus/i 2 c configuration. when the soc has completed configuring the device, it must write to register 0xff to end the configuration. 5.1.6 otp configuration stage (otp_cfg) once the soc has indicated that it is done with configuration, all configuration data is combined in this stage. the default data, the soc configur ation data, and the otp data are all combined in the firmware and the device is pro- grammed. after the device is fully configured, it will go idle and then into suspend if there is no vbus or hub.connect present. once vbus is present, and battery charging is enabled, the device will transition to the battery charger detection stage. if vbus is present, and battery charging is not enabled, the device will transition to the connect stage. 5.1.7 hub connect stage (hub.connect) once the chgdet stage is completed, the device enters the hub connect stage. usb connect can be initiated by asserting the vbus pin function high. the device will remain in the hub connect stage indefinitely until the vbus pin function is deasserted.
usb5744 ds00001855d-page 22 ? 2015-2016 microchip technology inc. 5.1.8 normal mode lastly, the hub enters normal mode of ope ration. in this stage full usb operation is supported under control of the usb host on the upstream port. the device will remain in the normal mode until the operating mode is changed by the sys- tem. if reset_n is asserted low, then standby mode is entered. the device may then be placed into any of the designated hub stages. asserting a soft disconnect on the upstream port will cause the hub to return to the hub.connect stage until the soft disconnect is negated.
? 2015-2016 microchip technology inc. ds00001855d-page 23 usb5744 6.0 device configuration the device supports a large number of features (some mutually ex clusive), and must be configured in order to correctly function when attached to a usb host controller. the hub can be configured either internal ly or externally depending on the implemented interface. microchip provides a comprehensive software programming tool, pro-touch, for configuring the usb5744 functions, registers and otp memory. all configuration is to be performed via the pro-touch programming tool. for additional infor- mation on the pro-touch programming tool, refer to the so ftware libraries within the microchip usb5744 product page at www.microchip.com/usb5744. 6.1 customer accessible functions the following usb or smbus accessible functions are avail able to the customer via the pro-touch programming tool. 6.1.1 usb accessible functions 6.1.1.1 otp access over usb the otp rom in the device is accessible via the usb bus. all otp parameters can be modified to the usb host. the otp operates in single ended mode. for more information, refer to the microchip usb5744 product page and sdk at www.microchip.com/usb5744 6.1.1.2 battery charging access over usb the battery charging behavior of the device can be dynamically changed by t he usb host when something other than the preprogrammed or otp programmed behavior is desired. for more information, refer to the microchip usb5744 product page and sdk at www.microchip.com/usb5744 6.1.2 smbus acc essible functions otp access and configuration of specific device function s are possible via the usb5744 smbus. all otp parameters can be modified via the smbus host. the otp can be programm ed to operate in single-ended, differential, redundant, or differential redundant mode, depending on the level of re liability required. for more information, refer to an1903 - ?configuration options for the usb5734 and usb5744? application note at www.microchip.com/an1903. note: device configuration straps and programmable pins are detailed in section 3.4, "configuration straps and programmable functions," on page 16 . refer to section 7.0, "device interfaces" for detailed information on each device interface. note: for additional programming details, refer to the pro-touch programming tool.
usb5744 ds00001855d-page 24 ? 2015-2016 microchip technology inc. 7.0 device interfaces the usb5744 provides multiple interfaces for configuration and external memory access. this section details the vari- ous device interfaces and their usage: ? spi master interface ? smbus slave interface 7.1 spi master interface the device is capable of code execution from an external spi rom. when configured for spi mode, on power up the firmware looks for an external spi flash device that contains a valid signature of 2dfu (device firmware upgrade) begin- ning at address 0xfffa. if a valid signature is found, then the external rom is enabled and the code execution begins at address 0x0000 in the external spi device. if a valid sig nature is not found, then exec ution continues from internal rom. 7.2 smbus slave interface the device includes an integrated smbus sl ave interface, which can be used to a ccess internal device run time registers or program the internal otp memory. smbus slave detection is accomplished by detection of pull-up resistors on both the smdat and smclk signals. refer to section 3.4.1, "spi/s mbus configuration" for additional information. note: for details on how to enable each interface, refer to section 3.4.1, "spi/smbus configuration" . for information on device connections, refer to section 4.0, "device connections" . for information on device configuration, refer to section 6.0, "dev ice configuration" . microchip provides a comprehensive software programming tool, pro-touch, for configuring the usb5744 functions, registers and otp memory. all configurat ion is to be performed via the pro-touch programming tool. for additional information on the pro-touch prog ramming tool, refer to software libraries within micro- chip usb5744 product page at www.microchip.com/usb5744. note: for spi timing info rmation, refer to section 9.6.7, "spi timing" . note: all device configuration must be performed via the pr o-touch programming tool. for additional information on the pro-touch programming tool, refer to software libraries within microchip usb5744 product page at www.microchip.com/usb5744.
? 2015-2016 microchip technology inc. ds00001855d-page 25 usb5744 8.0 functional descriptions this section details various usb5744 functions, including: ? downstream battery charging ? resets ? link power management (lpm) ? port control interface 8.1 downstream battery charging the device can be configured by an oem to have any of t he downstream ports support battery charging. the hub?s role in battery charging is to provide ackno wledgment to a device?s query as to w hether the hub system su pports usb battery charging. the hub silicon does not provide any current or powe r fets or any additional circuitry to actually charge the device. those components must be provided externally by the oem. if the oem provides an external supply capable of supplying current per the batte ry charging specification, the hub can be configured to indicate the presence of such a supply from the device. this indication, via the prt_ctl[4:1] pins, is on a per port basis. for example, the oem can configure tw o ports to support battery charging through high current power fets and leave the other two ports as standard usb ports. for additional information, refer to the microchip usb5744 battery charging application note on the microchip.com usb5744 product page at www.microchip.com/usb5744. figure 8-1: battery charging external power supply soc vbus[n] prt_ctl[n] int scl sda microchip hub dc power
usb5744 ds00001855d-page 26 ? 2015-2016 microchip technology inc. 8.2 resets the device includes the followin g chip-level reset sources: ? power-on reset (por) ? external chip reset (reset_n) ? usb bus reset 8.2.1 power-on reset (por) a power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the device. a timer within the device will assert the internal reset per the specifications listed in section 9.6.2, "power-on and configuration strap timing," on page 35 . 8.2.2 external chip reset ( reset_n ) a valid hardware reset is defined as assertion of reset_n , after all power supplies are within operating range, per the specifications in section 9.6.3, "reset and config uration strap timing," on page 36 . while reset is asserted, the device (and its associated external circuitry) ente rs standby mode and c onsumes minimal current. assertion of reset_n causes the following: 1. the phy is disabled and the differential pairs will be in a high-impedance state. 2. all transactions immediately te rminate; no states are saved. 3. all internal registers return to the default state. 4. the external crystal oscillator is halted. 5. the pll is halted. 8.2.3 usb bus reset in response to the upstream port signaling a rese t to the device, the device performs the following: 1. sets default address to 0. 2. sets configuration to unconfigured. 3. moves device from suspended to active (if suspended). 4. complies with the usb specification for behavior after completion of a reset sequence. the host then configures the device in accordance with the usb specification. 8.3 link power management (lpm) the device supports the l0 (on), l1 (sleep), and l2 (sus pend) link power management st ates. these supported lpm states offer low transitional latencies in the tens of microseconds ve rsus the much longer latenc ies of the traditional usb suspend/resume in the tens of milliseconds . the supported lpm states are detailed in table 8-1 . note: all power supplies must have reach ed the operating levels mandated in section 9.2, "operating condi- tions**," on page 31 , prior to (or coincident with) the assertion of reset_n . note: the device does not propagate the upstre am usb reset to downstream devices. table 8-1: lpm state definitions state description entry/exit time to l0 l2 suspend entry: ~3 ms exit: ~2 ms (from start of resume) l1 sleep entry: <10 us exit: <50 us l0 fully enabled (on) -
? 2015-2016 microchip technology inc. ds00001855d-page 27 usb5744 8.4 port control interface port power and over-current sense share the same pin ( prt_ctlx ) for each port. these functions can be controlled directly from the usb hub, or via the processor. the device can be configured into the following port control modes: ? ganged mode ? combined mode port connection in various modes are detailed in the following subsections. 8.4.1 port connection in ganged mode in this mode, one pin ( gang_pwr ) is used to control port power and over-current sensing. 8.4.2 port connection in combined mode 8.4.2.1 port power contro l using usb power switch when operating in combined mode, the device will have one port power control and over-current sense pin for each downstream port. when disabling port power, the driver will ac tively drive a '0'. to avoid unnecessary power dissipation, the pull-up resistor will be disabled at that time. when port power is enabled, it will disable the output driver and enable the pull-up resistor, making it an open drain output. if there is an over-current situation, the usb power switch will assert the open drain ocs signal. the schmidt trigger input will reco gnize that as a low. the open drain output does not inter- fere. the over-current sense filter handles the transient conditions such as low voltage while the device is powering up. when the port is enabled, the prt_ctlx pin input is constantly sampled. overcurrent events can be detected in one of two ways: ? single, continuous low pulse (consecutive low samples over t ocs_single ), as shown in figure 8-3 . ? two short low pulses within a rolling window (two groupings of 1 or more low samples over t ocs_double ), as shown in figure 8-4 . figure 8-2: port power control with usb power switch figure 8-3: single low pulse overcurrent detection usb power switch 50k prtpwr en ocs ocs pull-up enable 5v usb device filter prt_ctlx prt_ctlx is v il t ocs_single
usb5744 ds00001855d-page 28 ? 2015-2016 microchip technology inc. 8.4.2.2 port power control using poly fuse when using the device with a poly fuse, t here is no need for an output power control. to maintain consistency, the same circuit will be used. a single port power control and over-cu rrent sense for each downstream port is still used from the hub's perspective. when disabling port power, the driver will acti vely drive a '0'. this will have no effect as the external diode will isolate pin from the load. when port power is ena bled, it will disable the output driver and enable the pull-up resistor. this means that the pull-up resist or is providing 3.3 volts to the anode of the diode. if there is an over-current situation, the poly fuse will open. this will cause the cathode of the diode to go to 0 volts. the anode of the diode will be at 0.7 volts, and the schmidt trigger input will register this as a low resulting in an over-current detection. the open drain output does not interfere. figure 8-4: double low pul se overcurrent detection table 8-2: overcurrent pulse timing symbol description min max units t ocs_single single low pulse assertion time 5 - ms t ocs_double double low pulse window - 20 ms note: the usb 2.0 and usb 3.1 gen 1 bpwron2pwrgood de scriptors must be set to 0 when using poly-fuse mode. refer to microchip application note an1903 ?c onfiguration options for the usb5734 and usb5744? for details on how to change these values. figure 8-5: port power control using a poly fuse prt_ctlx is v il t ocs_double prt_ctlx 50k prtpwr ocs usb device pull-up enable 5v poly fuse filter
? 2015-2016 microchip technology inc. ds00001855d-page 29 usb5744 8.4.2.3 port power control with single poly fuse and multiple loads many customers use a single poly fuse to power all their dev ices. for the ganged situation, all power control pins must be tied together. 8.4.3 port controller connection example figure 8-6: port power control with ganged control with poly fuse figure 8-7: usb5744 with 4 generic port power controllers (2 bc enabled) pull-up enable usb device poly fuse 5v pull-up enable pull-up enable 50k 50k 50k prtpwr ocs usb device usb device prt_ctlx prt_ctly prt_ctlz usb5744 port 1 connector generic port power controller power (high current) (bc enabled) ocs d+ d - vbus d+ d- port 2 connector generic port power controller power (high current) (bc enabled) ocs d+ d - vbus d+ d- prt_ctl2 prt_ctl1 port 3 connector generic port power controller power ocs d+ d - vbus d+ d- prt_ctl3 port 4 connector generic port power controller power ocs d+ d - vbus d+ d- prt_ctl4
usb5744 ds00001855d-page 30 ? 2015-2016 microchip technology inc. note: the cfg_bc_en configuration strap must be properly config ured to enable battery charging on the appro- priate ports. for example, in the application shown in figure 8-7 , cfg_bc_en must be connected to an external 10 k ? pull-down resistor to enable battery charging on ports 1 and 2. for more information on the cfg_bc_en configuration strap, refer to section 3.4.4, "battery charging configuration (cfg_bc_en)" .
? 2015-2016 microchip technology inc. ds00001855d-page 31 usb5744 9.0 operational characteristics 9.1 absolute maximum ratings* +1.2 v supply voltage ( vdd12 ) ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to +1.32 v +3.3 v supply voltage ( vdd33 ) ( note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to +4.6 v positive voltage on input signal pins, with respect to ground ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.6 v negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v positive voltage on xtali/clk_in , with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+3.63 v positive voltage on usb dp/dm signal pins, with respect to grou nd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6.0 v positive voltage on usb 3.1 gen 1 usb3up_ xxxx and usb3dn_ xxxx signal pins, with respect to ground . . . . .1.32 v storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125 o c lead temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 hbm esd performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kv note 1: when powering this device from laboratory or system powe r supplies, it is important that the absolute max- imum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exis ts, it is suggested to use a clamp circuit. note 2: this rating does not apply to the following pins: all usb dm/dp pins, xtal1/clk_in , and xtalo *stresses exceeding those listed in th is section could cause permanent damage to the device. this is a stress rating only. exposure to absolute maximum rating conditions for extended periods may affect device reliability. functional operation of the device at any condit ion exceeding those indicated in section 9.2, "operating conditions**" , section 9.5, "dc specifications" , or any other applicable section of this specification is not implied. 9.2 operating conditions** +1.2 v supply voltage ( vdd12 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.08 v to +1.32 v +3.3 v supply voltage ( vdd33 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 v to +3.6 v input signal pins voltage ( note 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +3.6 v xtali/clk_in voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +3.6 v usb 2.0 dp/dm signal pins voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +5.5 v usb 3.1 gen 1 usb3up_ xxxx and usb3dn_ xxxx signal pins voltage . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +1.32 v ambient operating temperature in still air (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 3 +1.2 v supply voltage rise time (t rt in figure 9-1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 s +3.3 v supply voltage rise time (t rt in figure 9-1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 s note 3: 0 o c to +70 o c for commercial version, -40 o c to +85 o c for industrial version. **proper operation of the device is guaranteed onl y within the ranges specified in this section. note: do not drive input signals without power supplied to the device.
usb5744 ds00001855d-page 32 ? 2015-2016 microchip technology inc. 9.3 package thermal specifications figure 9-1: supply rise time model table 9-1: package thermal parameters symbol c/w velocity (meters/s) ? ja 30 0 26 1 ? jt 0.2 0 0.3 1 ? jc 2.6 0 2.6 1 note: thermal parameters are measured or estimated fo r devices in a multi-layer 2s2p pcb per jesdn51. table 9-2: maximum power dissipation parameter value units pd(max) 1400 mw t 10% 10% 90% voltage t rt t 90% time 100% 3.3 v vss vdd33 90% 100% 1.2 v vdd12
? 2015-2016 microchip technology inc. ds00001855d-page 33 usb5744 9.4 power consumption this section details the power consumption of the device as measured during various modes of operation. power dis- sipation is determined by temperature, supply voltage, and external source/sink requirements. table 9-3: device power consumption typical (ma) typical power vdd33 vdd12 (mw) reset 0.8 1.8 4.8 no vbus 2.0 5.0 12.6 global suspend 2.0 5.2 12.9 4 fs ports 39 35 170 4 hs ports 53 42 222 4 ss ports 55 683 1001 4 ss/hs ports 93 688 1132
usb5744 ds00001855d-page 34 ? 2015-2016 microchip technology inc. 9.5 dc specifications note 4: xtali can optionally be driven from a 25 mhz singled-ended clock oscillator. note 5: refer to the usb 3.1 gen 1 specification for usb dc electrical characteristics. table 9-4: i/o dc electrical characteristics parameter symbol min typical max units notes i type input buffer low input level high input level v il v ih 2.1 0.9 v v is type input buffer low input level high input level schmitt trigger hysteresis (v iht - v ilt ) v il v ih v hys 1.9 920 0.9 40 v v mv o6 type output buffer low output level high output level v ol v oh vdd33 -0.4 0.4 v v i ol = 6 ma i oh = -6 ma o12 type output buffer low output level high output level v ol v oh vdd33 -0.4 0.4 v v i ol = 12 ma i oh = -12 ma od12 type output buffer low output level v ol 0.4 v i ol = 12 ma iclk type input buffer ( xtali input) low input level high input level v il v ih 0.85 0.50 vdd33 v v note 4 io-u type buffer ( see note 5 ) note 5
? 2015-2016 microchip technology inc. ds00001855d-page 35 usb5744 9.6 ac specifications this section details the various ac timing specifications of the device. 9.6.1 power supply and reset_n sequence timing figure 9-2 illustrates the recommended power supply sequencing and timing for the device. vdd33 should rise after or at the same rate as vdd12 . similarly, reset_n and/or vbus_det should rise after or at the same rate as vdd33 . vbus_det and reset_n do not have any other timing dependencies. 9.6.2 power-on and configuration strap timing figure 9-3 illustrates the configuration strap valid timing require ments in relation to power-on, for applications where reset_n is not used at power-on. in order for valid configur ation strap values to be read at power-on, the following timing requirements must be met. the operational levels (v opp ) for the external power supplies are detailed in section 9.2, "operating cond itions**," on page 31 . device configuration straps are also latched as a result of reset_n assertion. refer to section 9.6.3, "reset and con- figuration strap timing" for additional details. figure 9-2: power supply a nd reset_n sequence timing table 9-5: power supply a nd reset_n sequence timing symbol description min typ max units t vdd33 vdd12 to vdd33 rise time 0 ms t reset vdd33 to reset_n / vbus_det rise time 0 ms figure 9-3: power-on config uration strap valid timing table 9-6: power-on configura tion strap latching timing symbol description min typ max units t csh configuration strap hold after external power supplies at opera- tional levels 1ms vdd12 vdd33 reset_n/ vbus_det all external power supplies v opp configuration straps t csh
usb5744 ds00001855d-page 36 ? 2015-2016 microchip technology inc. 9.6.3 reset and configuration strap timing figure 9-4 illustrates the reset_n pin timing requirements and its relation to the configuration strap pins. assertion of reset_n is not a requirement. however, if used, it must be asserted for the minimum period specified. refer to section 8.2, "resets" for additional information on resets. refer to section 3.4, "configuration straps and programmable func- tions" for additional information on configuration straps. 9.6.4 usb timing all device usb signals conform to the voltage, power, and timing characteristics/specifications as set forth in the uni- versal serial bus specification . please refer to the universal serial bus revision 3.1 specification , available at http:// www.usb.org/developers/docs. 9.6.5 i 2 c timing all device i 2 c signals conform to the 400khz fast mode (fm) volt age, power, and timing characteristics/specifications as set forth in the i 2 c-bus specification . please refer to the i 2 c-bus specification , available at http://www.nxp.com/doc- uments/user_manual/um10204.pdf. 9.6.6 smbus timing all device smbus signals conform to the voltage, power, and ti ming characteristics/specificat ions as set forth in the sys- tem management bus specification. please refer to the system management bus specification , version 1.0, available at http://smbus.org/specs. figure 9-4: reset_n conf iguration strap timing table 9-7: reset_n configuration strap timing symbol description min typ max units t rstia reset_n input assertion time 5 ? s t csh configuration strap pins hold after reset_n deassertion 1 ms note: the clock input must be stable prior to reset_n deassertion. configuration strap latching and output drive timing s shown assume that the power-on reset has finished first otherwise the timings in section 9.6.2, "power-on and configuration strap timing" apply. reset_n configuration straps t rstia t csh
? 2015-2016 microchip technology inc. ds00001855d-page 37 usb5744 9.6.7 spi timing this section specifies the spi ti ming requirements for the device. figure 9-5: spi timing table 9-8: spi timing (30 mhz operation) symbol description min typ max units t fc clock frequency 30 mhz t ceh chip enable ( spi_ce_en ) high time 100 ns t clq clock to input data 13 ns t dh input data hold time 0 ns t os output setup time 5 ns t oh output hold time 5 ns t ov clock to output valid 4 ns t cel chip enable ( spi_ce_en ) low to first clock 12 ns t ceh last clock to chip enable ( spi_ce_en ) high 12 ns table 9-9: spi timing (60 mhz operation) symbol description min typ max units t fc clock frequency 60 mhz t ceh chip enable ( spi_ce_en ) high time 50 ns t clq clock to input data 9 ns t dh input data hold time 0 ns t os output setup time 5 ns t oh output hold time 5 ns t ov clock to output valid 4 ns t cel chip enable ( spi_ce_en ) low to first clock 12 ns t ceh last clock to chip enable ( spi_ce_en ) high 12 ns spi_clk spi_di spi_do spi_ce_n t cel t fc t clq t ceh t dh t oh t os t ov t oh
usb5744 ds00001855d-page 38 ? 2015-2016 microchip technology inc. 9.7 clock specifications the device can accept either a 25mhz crystal or a 25mhz si ngle-ended clock oscillator (50ppm) input. if the single- ended clock oscillator method is implemented, xtalo should be left unconnected and xtali/clk_in should be driven with a nominal 0-3.3v clock signal. the input cloc k duty cycle is 40% minimum, 50% typical and 60% maximum. it is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals ( xtali / xtalo ). the following circuit design ( figure 9-6 ) and specifications ( ta b l e 9 - 1 0 ) are required to ensure proper operation. 9.7.1 crystal specifications it is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals ( xtali / xtalo ). refer to table 9-10 for the recommended crystal specifications. note 6: frequency deviation over time is also referred to as aging. figure 9-6: 25mhz crystal circuit table 9-10: crystal specifications parameter symbol min nom max units notes crystal cut at, typ crystal oscillation mode fundamental mode crystal calibration mode parallel resonant mode frequency f fund - 25.000 - mhz frequency tolerance @ 25 o cf tol - - 50 ppm note 6 frequency stability over temp f temp - - 50 ppm note 6 frequency deviation over time f age - 3 to 5 - ppm total allowable ppm budget - - 100 ppm note 7 shunt capacitance c o - 7 typ - pf load capacitance c l - 20 typ - pf drive level p w 100 - - uw equivalent series resistance r 1 --50 ? operating temperature range note 7 - note 8 o c xtali/clk_in pin capacitance - 3 typ - pf note 9 xtalo pin capacitance - 3 typ - pf note 9 usb5742 xtalo xtali y1 c 1 c 2
? 2015-2016 microchip technology inc. ds00001855d-page 39 usb5744 note 7: 0 c for commercial version, -4 0 c for industrial version. note 8: +70 c for commercial version, +85 c for industrial version. note 9: this number includes the pad, the bond wire and the lead frame. pcb capacitance is not included in this value. the xtali/clk_in pin, xtalo pin and pcb capacitance values are required to accurately calcu- late the value of the two external load capacitors. these two external load capacitors determine the accu- racy of the 25.000 mhz frequency. 9.7.2 external reference clock ( clk_in ) when using an external reference clock, the fo llowing input clock specif ications are suggested: ?25mhz ? 50% duty cycle 10%, 100 ppm ? jitter < 100 ps rms
usb5744 ds00001855d-page 40 ? 2015-2016 microchip technology inc. 10.0 package information 10.1 package marking information * standard device marking consists of microchip part number, year code, week code and traceability code. for device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: i temperature range designator (blank = commercial, i = industrial) r product revision nnn internal code e3 pb-free jedec ? designator for matte tin (sn) v plant of assembly coo country of origin yy year code (last two digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note: in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custom er-specific information. 56-vqfn (7x7 mm) pin 1 usb5744 i rnnn e3 vcoo yywwnnn e3
? 2015-2016 microchip technology inc. ds00001855d-page 41 usb5744 10.2 package drawings note: for the most current package drawings, se e the microchip packaging specification at: http://www.microchip.com/packaging. figure 10-1: 56-vqfn package (drawing)
usb5744 ds00001855d-page 42 ? 2015-2016 microchip technology inc. figure 10-2: 56-vqfn package (dimensions)
? 2015-2016 microchip technology inc. ds00001855d-page 43 usb5744 figure 10-3: 56-vqfn land pattern
usb5744 ds00001855d-page 44 ? 2015-2016 microchip technology inc. appendix a: data sheet revision history table a-1: revision history revision level & date section/figure/entry correction ds00001855d (06-02-16) section 10.0, package information added top marking information and land pat- tern drawing. all updated ?sqfn? references to ?vqfn?. name change only. section 8.4.2.1, port power control using usb power switch added additional information on overcurrent detection methods. section 9.6.1, po wer supply and reset_n sequence timing added power supply and reset_n sequence timing section. section 9.6.5, i2c timing ?100khz standard mode (sm)? updated to ?400khz fast mode (fm)?, since the device supports up to 400khz i 2 c operation. ds00001855c (06-22-15) all ? updated ?usb 3.0? references to ?usb 3.1 gen 1? throughout the document ? updated usb specification references ? misc. typos ds00001855b (04-16-15) features changed en vironmental feature bullet from ?4kv hbm jesd22-a114f esd protection? to ?3kv hbm jesd22-a114f esd protection? section 9.2, operating conditions** changed xtali/clk_in voltage to -0.3v to +3.6v table 9-10, "crystal specifications" total allowable ppm budget changed to 100pm, removed notes under table regarding ?frequency tolerance? and ?frequency and transmitter clock frequency? section 9.7.2, external reference clock (clk_in) changed +-350ppm t +-100 ppm figure 3-1, "56-vqfn pin assignments"table 3-1, "56-vqfn pin assignments" modified pin 32 from ?prt_ctl4/ gang_pwr? to ?prt_ctl4/gang_pwr ? table 3-5, "usb port control pin descriptions" revised description of pin 1, gang_pwr table 1-1, "general terms" and throughout document replaced the term hub controller with hub feature controller, added definition in ta b l e 1 - 1, "general terms" . section 6.1.2, smbus accessible functions added web link to an1903 removed portmap feat ure throughout docu- ment. table 3-7, "miscellaneous pin descriptions" modified reset_n pin description section 8.3, link power management (lpm) removed ?per the usb 3.0 specification? from the first sentence. re moved last sentence ?for additional information, refer to the usb 3.0 specification.? table 9-2, "maximum power dissipa- tion" added ta b l e 9 - 2 .
? 2015-2016 microchip technology inc. ds00001855d-page 45 usb5744 section 9.7, "clock specifications" , figure 9-6 , table 9-10, "crystal specifications" updated these sections. section 9.7.2, external reference clock (clk_in) oscillator changed from ?35mhz? to ?25 mhz? section 9.6.7, spi timing removed spi interface configure note section 9.1, absolute maximum rat- ings* added ?positive voltage on usb 3.0 usb3up- _ xxxx and usb3dn_ xxxx signal pins, with respect to ground...1.32 v changed xtali positive voltage from 2.1v to 3.63v. changed ?usb 3.0 dp/dm signal pins volt- age? to ?usb 3.0 usb3up_ xxxx and usb3dn_ xxxx signal pins voltage? section 8.4.2, "port connection in combined mode," on page 27 added note under section 8.4.2 product identification system on page 47 updated ordering information section 9.1, "absolute maximum rat- ings*," on page 31 updated +1.2v supply voltage absolute max value. added hbm esd performance specifi- cation. table 9-1, ?package thermal parame- ters,? on page 32 added package thermal parameters. worldwide sales and service updated worldwide sales listing table 9-4, ?i/o dc electrical charac- teristics,? on page 34 updated i buffer type high input level max. added is buffer type schmitt trigger hystere- sis values. cover, all updated document title to ?4-port ss/hs con- troller hub? removed portmap references. removed sentence: ?these circuits are used to detect the attachment and type of a usb charger and provide an in terrupt output to indi- cate charger information is available to be read from the device?s status registers via the serial interface.? figure 3-1: 56-vqfn pin assign- ments on page 8 added configuration strap note under figure. ds00001855a (12-15-14) all initial release table a-1: revision history (continued) revision level & date section/figure/entry correction
usb5744 ds00001855d-page 46 ? 2015-2016 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep custom ers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://www.microchip.com/support
? 2015-2016 microchip technology inc. ds00001855d-page 47 usb5744 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: usb5744 tape and reel option: blank = standard packaging (tray) t = tape and reel ( note 1 ) temperature range: blank = 0 ? c to +70 ? c (commercial) i= -40 ? c to +85 ? c (industrial) package: 2g = 56-pin vqfn examples: a) usb5744/2g tray, commercial temp., 56-pin vqfn b) usb5744-i/2g tray, industrial temp., 56-pin vqfn c) usb5744t-i/2g tape & reel, industrial temp., 56-pin vqfn d) usb5744t/2g tape & reel, commercial temp., 56-pin vqfn note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. part no. device tape & reel / temperature range xx [x] [-x] package option
usb5744 ds00001855d-page 48 ? 2015-2016 microchip technology inc. information contained in this publication re garding device applications and the like is provided only for your convenience and may be super- seded by updates. it is your responsibilit y to ensure that your application meets wi th your specifications. microchip makes no rep- resentations or warranties of any kind whether ex press or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entire ly at the buyer?s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, cl aims, suits, or expenses resulting from such use. no licens es are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip l ogo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, klee r, lancheck, link md, medialb, most, most logo, mplab, optolyze r, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered tradem arks of microchip technology incorporat ed in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, body com, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit se rial programming, icsp, inter-c hip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem. net, pickit, pictail, puresilicon, righttouc h logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of mi crochip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of micr ochip technology germany ii gmbh & co. kg, a subsidiary of microc hip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015-2016, microchip technology incorporated, pr inted in the u.s.a., all rights reserved. isbn: 9781522406624 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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